This invention relates generally to a method for making a CMOS integrated device, and more specifically to a method for fabricating an LDD CMOS device using a minimum of mask steps.
The fabrication of semiconductor devices is becoming an evermore complex process. As the complexity of the devices increases, more and more processing steps are required to fabricate the desired device. Each processing step that is added to the process, however, increases the cost of manufacture and also reduces the yield of the manufactured device. In designing a manufacturing process, therefore, it is desirable to minimize the number of process steps, and especially to minimize the number of lithography masking steps.
The CMOS device structure has now become the most widely used semiconductor device structure. The process for manufacturing CMOS devices inherently has a large number of steps because of the necessity for separately manufacturing both N channel devices and P channel devices. In addition, many CMOS device implementations require an LDD (lightly doped drain) structure which can add further to the number of process steps required. With the objective of providing a manufacturable CMOS process having a minimum number of processing steps, a need existed for a simplified CMOS process.
It is therefore an object of this invention to provide an improved LDD CMOS process.
It is a further object of this invention to provided an improved LDD CMOS process with a reduced number of processing steps and especially a reduced number of lithography processing steps.